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AD7709 a rev. pra january 2001 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? ? ? ? ? analog devices, inc., 2001 16-bit sigma delta adc with current sources, switchable reference inputs and i/o port preliminary technical data preliminary technical data 16-bit single channel sigma delta-adc factory calibrated (field calibration not required) output settles in one conversion cycle (single conver sion mode) programmable gain front end 16-bit no missing codes 13-bit pk-pk resolution @ 20hz, 20mv range 16-bit pk-pk resolution @ 20hz, 2.56v range interface three-wire serial spi tm , qspi tm , microwire tm and dsp compatible schmitt trigger on sclk power specified for single 3v and 5v operation normal : 2ma @ 3v powerdown : 20ua (32khz crystal running) on-chip functions rail-to-rail input buffer and pga switchable reference inputs 3 configurable current sources low side power swtches digital i/o port applications industrial process control instrumentation pressure transducers portable instrumentation functional block diagram general description the AD7709 is a complete analog front-end for low frequency measurement applications. the AD7709 contains a 16-bit sigma delta adc with pga and can be configured as 2 fully-differential input channels or 4 pseudo-differential input channels. inputs signal ranges from 20mv to 2.56v can be directly converted using the AD7709. these signals can be converted directly from a transducer without the need for signal conditioning. other on-chip features include three software configurable current sources, switchable reference inputs, low side power switches and a 4-bit digital i/o port. the device operates from a 32khz crystal with an on- board pll generating the required internal operating frequency. the output data rate from the part is software programmable. the pk-pk resolution from the part varies with the programmed gain and output data rate. the part operates from a single +3v or +5v supply. when operating from +3v supplies, the power dissipation for the part is xmw. the AD7709 are housed in a 24- pin soic and tssop packages. ? spiand qspi are a registered trademark of motorola inc. ? microwire is a registered trademark of national semiconductor corp. features xtal1 xtal2 refin2(+) refin2(-) vdd osc . & pll refin1(+) refin1(-) sw2/p2 sw1/p1 gnd AD7709 i/o port vdd ain1 iout 1 iout 2 ain2 ain3 / p3 ain4 / p4 mux buf pga aincom serial interface & control logic dout din sclk cs rdy reset 16-bit s - d adc i1 i2 i3 pwrgnd
C2 C re v . p ra j anuary 2 0 0 1 AD7709-specifications 1 (v dd = +3v or +5.0v , refin(+) = +2.5v; refin(-) = 0v; xtal1/xtal2 = 32 khz crystal; all specifications t min to t max unless otherwise noted.) preliminary technical data parameter b grade units test conditions output update rate 5.4 hz min. 105 hz max. 0.021hz (0.732msec.) increments no missing codes 16 bits min. resolution 13 bits pk-pk +20mv range, 20hz update rate 16 bits pk-pk +2.56v range, 20hz update rate output noise and update rates see tables below in adc description integral nonlinearity 15 ppm of fsr max. offset error t b d offset error drift vs temp 10 nv/c typ. offset error drift vs time t b d nv/1000 hours typ. gain error t b d gain error drift vs temp 1 ppm/ctyp. gain error drift vs time t b d ppm/1000 hours typ. power supply rejection(psr) 90 db min. input range = 20mv 90 db min. input range = 2.56v common mode rejection(cmr) on ain 90 db min. at dc, range = 20mv on ain 90 db min. at dc, range = 2.56v on refin 90 db min. at dc, range = 20mv on refin 90 db min. at dc, range = 2.56v analog input current dc bias current 1 na max. dc bias current drift t b d na typ. dc offset current t b d na typ. dc offset current drift t b d na typ. reference inputs (refin1& refin2) normal mode 50hz/60hz rejection 60 db min. reference dc input current t b d a typ. refin(+) to refin(-) voltage +2.5v nom. refin referes to both refin1 and refin2 refin(+) to refin(-) range + 1 v min. v dd v max. refin common mode range gnd-30mv v min. v dd +30mv v max. refin common mode 50/60hz rejection t b d db min. analog inputs normal mode 50hz/60hz rejection 60 db min. 50/60hz 1hz , 20hz update rate common mode 50/60hz rejection 90 db min. 50/60hz 1hz, range = 20mv 90 db min. 50/60hz 1hz, range = 2.5v differential input voltage ranges refin/gain v nom. refin refers to both refin1 and refin2. refin=refin(+ )-refin(-) gain=1to 128. pseudo-differential input voltage ranges 0v to refin/gain v nom. full-scale range matching 5 uv typ. absolute ain voltage limits buffered inputs gnd+50mv v min. v dd -50mv v max unbuffered inputs gnd-30mv vmin v dd +30mv vmax
C3C rev. pra january 2001 AD7709 preliminary technical data logic inputs all inputs except sclk and xtal1 v inl , input low voltage 0.8 v max. v dd = 5v v inl , input low voltage 0.4 v max. v dd = 3v v inh , input high voltage 2.0 v min. v dd = 3v or 5v sclk only (schmitt triggered input) v t(+) 1.4/3 v min/v max v dd = 5v v t(-) 0.8/1.4 v min/v max v dd = 5v v t(+)- v t(-) 0.4/0.85 v min/v max v dd = 5v v t(+) 0.95/2.5 v min/v max v dd = 3v v t(-) 0.4/1.1 v min/v max v dd = 3v v t(+)- v t(-) 0.4/0.85 v min/v max v dd = 3v xtal1 only v inl , input low voltage 0.8 v max. v dd = 5v v inh , input high voltage 3.5 v min. v dd = 5v v inl , input low voltage 0.4 v max. v dd = 3v v inh , input high voltage 2.5 v min. v dd = 3v input currents 10 a max. v in = 0v or v dd input capacitance 10 pf typ. all digital inputs logic outputs (excluding xtal2) v oh , output high voltage v dd - 0.6 v min. v dd = 3v, i source = 100a v ol , output low voltage 0.4 v max. v dd = 3v, i sink = 100a v oh , output high voltage 4 v min. v dd = 5v, i source = 200a v ol , output low voltage 0.4 v max. v dd = 5v, i sink = 1.6ma floating state leakage current 10 ua max. floating state output capacitance 10 pf typ. data output coding binary unipolar mode offset binary bipolar mode excitation current sources i1 and i2 output current 200 a nom. i3 output current 25 a nom. initial tolerance at 25c 10 % typ. drift 20 ppm/c typ. initial current matching at 25c 1 % matching between i1 and i2 drift matching 1 ppm/c typ. line regulation (v dd ) tbd na/v max. v dd = 5v10% load regulation tbd na/v max. output compliance av dd -0.5 v max. low-side power switches (sw1 and sw2) ron 5 w typ v dd = 5v 7 w typ v dd = 3v allowable current 20 ma max per switch system calibration full-scale calibration limit 1.05 x fs v max. zero-scale calibration limit -1.05 x fs v min. input span 0.8 x fs v min. 2.1 x fs v max. start up time from power-on 500 msec typ. from idle mode 1 msec. typ. from power-down mode 1 msec. typ. 500 msec. typ. osc. powered down power requirements power supply voltages v dd - gnd 2.7/3.6 v min/max v dd = 3v nom. 4.5/5.5 v min/max v dd = 5v nom. parameter b grade units test conditions
AD7709 C4C rev. pra january 2001 preliminary technical data parameter b grade units test conditions power supply currents v dd current (normal mode) t b d ma v dd =3v v dd current (normal mode) t b d ma v dd =5v v dd current (idle mode) t b d m a v dd =3v v dd current (idle mode) t b d m a v dd =5v v dd current (power-down mode) 20 a max. v dd =3v, 32.768khz osc. running v dd current (power-down mode) 30 a max. v dd =5v, 32.768khz osc. running notes 1 temperature range -40 c to +85 c 2 3 4
AD7709 C5C rev. pra january 2001 preliminary technical data ordering guide model temperature package package drawing range description option AD7709br -40c to +85c soic r-24 AD7709bru -40c to +85c tssop ru-24 1 stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd.............................................-0.3v to +7v analog input voltage to gnd...........-0.3v to v dd +0.3v reference input voltage to gnd.......-0.3v to v dd +0.3v ain/refin current (indefinite)...........................30ma digital input voltage to gnd...........-0.3v to v dd +0.3v digital output voltage to gnd........-0.3v to v dd +0.3v pwrgnd to gnd...............................-0.3v to +0.3v operating temperature range..................-40c to 85c storage temperature range....................-65c to 150c junction temperature........................................+150c package power dissipation........................tbd mw q ja thermal impedance..................................90c/w lead temperature, soldering vapor phase (60sec)..................................+215c infrared (15 sec).......................................+220c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7709 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. outline dimensions 24-lead plastic soic (r-24) 24-lead plastic tssop (ru-24) 24 13 12 1 0.6141 (15.60) 0.5985 (15.20) 0.4193 ( 10.65) 0.3937 ( 10.00) 0.2992 ( 7.60) 0.2914 ( 7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8? 0? 0.0291 (0.74) 0.0098 (0.25) x 45? 24-lead plastic tssop (ru-24)
AD7709 C6C rev. pra january 2001 preliminary technical data timing characteristics 1, 2 (v dd = +3v 10% or v dd = +5v 10%;gnd = 0 v:x tal = 32.768khz; input logic 0 = 0 v, logic 1 = v dd unless otherwise noted) limit at t min , t max parameter (b version) units conditions/comments t 1 32.768 khz typ crystal oscillator frequency. t 2 50 ns min reset pulse width read operation t 3 0 ns min rdy to cs setup time t 4 0 ns min cs falling edge to sclk active edge setup time 3 t 5 4 0 ns min sclk active edge to data valid delay 3 60 ns max v dd = +4.5 v to +5.5 v 80 ns max v dd = +2.7 v to +3.6 v t 5a 4, 5 0 ns min cs falling edge to data valid delay 3 60 ns max v dd = +4.5 v to +5.5 v 80 ns max v dd = +2.7 v to +3.6 v t 6 100 ns min sclk high pulse width t 7 100 ns min sclk low pulse width t 8 0 ns min cs rising edge to sclk inactive edge hold time 3 t 9 6 10 ns min bus relinquish time after sclk inactive edge 3 80 ns max t 10 100 ns max sclk active edge to rdy high 3, 7 write operation t 11 0 ns min cs falling edge to sclk active edge setup time 3 t 12 30 ns min data valid to sclk edge setup time t 13 25 ns min data valid to sclk edge hold time t 14 100 ns min sclk high pulse width t 15 100 ns min sclk low pulse width t 16 0 ns min cs rising edge to sclk edge hold time notes 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. 2 see figures 1 and 2. 3 sclk active edge is falling edge of sclk. 4 these numbers are measured with the load circuit of figure 3 and defined as the time required for the output to cross the v ol or v oh limits. 5 this specification only comes into play if cs goes low while sclk is low. it is required primarily for interfacing to dsp machines. 6 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figur e 3. the measured number is then extrapolated back to remove effects of charging or discharging the 50 pf capacitor. this means that the times quoted in the timing characteristics are the true bus relinquish tim es of the part and as such are independent of external bus loading capacitances. 7 rdy returns high after the first read from the device after an output update. the same data can be read again, if required, while rdy is high, although care should be taken that subsequent reads do not occur close to the next output update.
AD7709 C7C rev. pra january 2001 preliminary technical data din msb t 12 lsb t 13 sclk cs t 15 t 16 t 14 t 11 dout msb t 5 t 9 lsb t 5a sclk cs rdy t 7 t 8 t 6 t 4 t 3 t 10 t 6 figure 1. write cycle timing diagram figure 2. read cycle timing diagram
AD7709 C8C rev. pra january 2001 preliminary technical data pin configuration pin function description pin no mnemonic function 1 iout1 output for internal excitation current sources. a single current source or any combination of the internal current sources i1,i2 and i3 can be switched to this output. 2 iout2 output for internal excitation current sources. a single current source or any combination of the internal current sources i1,i2 and i3 can be switched to this output. 3 refin1(+) positive reference input. refin(+) can lie anywhere between v dd and gnd. the nominal reference voltage (refin(+)-refin(-)) is 2.5v but the part is functional with a reference range from 1v to v dd . 4 refin1(-) negative reference input. this reference input can lie anywhere between gnd and v dd -1v. 5 ain1 analog input channel 1. programmable-gain analog input which can be used as a pseudo-differential input when used with aincom or as the positive in- put of a fully-differential input pair when used with ain2. (see communica- tions register section) 6 ain2 analog input channel 2. programmable-gain analog input which can be used as a pseudo-differential input when used with aincom or as the negative input of a fully-differential input pair when used with ain1. (see communica- tions register section) 7 ain3/p3 analog input channel 3 or digital port bit. programmable-gain analog input which can be used as a pseudo-differential input when used with aincom or as the positive input of a fully-differential input pair when used with ain4. the second function of this bit is as a general purpose digital input bit. 8 ain4/p4 analog input channel 4 or digital port bit. programmable-gain analog input which can be used as a pseudo-differential input when used with aincom or as the negative input of a fully-differential input pair when used with ain3. the second function of this bit is as a general purpose digital input bit. 9 aincom all analog inputs are referenced to this input when configured in pseudo-dif- ferential input mode. 10 refin2(+) positive reference input. refin2(+) can lie anywhere between v dd and gnd. the nominal reference voltage (refin2(+)-refin2(-)) is 2.5v but the part is functional with a reference range from 1v to v dd . top view (not to scale) sclk cs reset ain1 aincom gnd v dd din dout drdy refin1(-) refin1(+) AD7709 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 xtal1 ain3/p3 ain 2 21 22 23 24 ain4/p4 refin2(+) p2/sw2 pwrgnd p1/sw1 xtal2 iout 1 iout 2 refin2(-)
AD7709 C9C rev. pra january 2001 preliminary technical data 11 refin2(-) negative reference input. this reference input can lie anywhere between gnd and v dd -1v. 12 p2/sw2 p2 can act as a general purpose input/output bit referenced between v dd and gnd or as a low-side power switch to pwrgnd.. 13 pwrgnd ground point for the low-side power switches sw2 and sw1. pwrgnd must be tied to gnd. 14 p1/sw1 p1 can act as a general purpose output bit referenced between v dd and gnd or as a low-side power switch to pwrgnd. 15 reset digital input used to reset the adc to its power-on-reset status. this pin has a weak pull-up internally to dv dd . 16 sclk serial clock input for data transfers to and from the adc. the sclk has a schmitt triggered input making the interface suitable for opto-isolated applica- tions. the serial clock can be continuous with all data transmitted in a con- tinuous train of pulses. alternatively, it can be noncontinuous clock with the information being transmitted to or from the AD7709 in smaller batches of data. 17 cs chip select input. this is an active low logic input used to select the AD7709. cs can be used to select the AD7709 in systems with more than one device on the serial bus or as a frame synchronisation signal in communicating with the device. cs can be hardwired low allowing the AD7709 to be operated in three-wire mode with sclk, din and dout used to interface with the device. 18 rdy rdy is a logic low status output from the AD7709. rdy is low if the adc has valid data in its data register. this output returns high on completion of a read operation from the data register. if data is not read, rdy will return high prior to the next update indicating to the user that a read operation should not be initiated. 19 d o u t serial data output with serial data being read from the output shift register of the adc. the output shift register can contain data from any of the on-chip data, calibration or control registers. 20 d i n serial data input with serial data being written to the input shift register on the AD7709. data in this shift register is transferred to the control registers within the adc depending on the selection bits of the communications regis- ter. 21 g n d ground reference point for the AD7709. 22 v dd supply voltage, 3v or 5v nominal. 23 xtal2 output from the 32khz crystal oscillator inverter. 24 xtal1 input to the 32khz crystal oscillator inverter.
AD7709 C10C rev. pra january 2001 preliminary technical data adc circuit information overview the AD7709 incorporates an analog multiplexer with a sigma-delta adc, on-chip programmable gain amplifier and digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain-gauge, pressure transducer or temperature measurement applications. the AD7709 offers 16-bit resolution. the AD7709 can be configured as 2 fully differential input channels or as 4 pseudo differential input channels referenced to aincom. the channel is buffered and can be programmed for one of 8 input ranges from +20mv to +2.56v. buffering the input channel means that the part can handle significant source impedances on the analog input and that r, c filtering (for noise rejection or rfi reduction) can be placed on the analog inputs if required. these input channels are intended to convert signals directly from sensors without the need for external signal conditioning. other functions contained on-chip that augment the operation of the adc include software configurable current sources, switchable reference inputs and low side power switches. the adc employs a sigma-delta conversion technique to realize up to 16-bits of no missing codes performance. the sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. a sinc 3 programmable low pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35hz (186.77ms) to 105.03hz (9.52ms). a chopping scheme is also employed to minimize adc channel offset errors. a block diagram of the adc input channel is shown in figure 3 below. 1 8 sf 3 digital output sinc 3 filter a in + v os a in os ch o p adc 1 2 -- - sf) xor - v ? ? () ff (8 3 s-d analog input buffer pga f chop f in f mod mux mod0 figure 3. AD7709 adc channel block diagram
AD7709 C11C rev. pra january 2001 preliminary technical data sf data update input range word rate (hz) 20mv 40mv 80mv 160mv 320mv 640mv 1.24v 2.56v 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 adc noise performance tables i and ii below show the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5lsb) for some typical output update rates . the numbers are typical and generated at a differential input voltage of 0v. the output update rate is selected via the sf7-sf0 bits in the filter register. it is important to note that the peak- to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. the output noise comes from two sources. the first is the electrical noise in the semiconductor devices (device noise) used in the implementation of the modulator. secondly, when the analog input is converted into the digital domain, quantization noise is added. the device noise is at a low level and is independant of frequency. the quantization noise starts at an even lower level but rises rapidly with increasing frequency to become the dominant noise source.the numbers in the tables are given for the bipolar input ranges. for the unipolar ranges the rms noise numbers will be the same as the bipolar range but the peak to peak resolution is now based on half the signal range which effectively means loosing 1 bit of resolution. table i. typical output rms noise vs. input range and update rate for AD7709 output rms noise in v sf data update input range word rate (hz) 20mv 40mv 80mv 160mv 320mv 640mv 1.24v 2.56v 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13 14 15 16 16 16 16 16 255 5.35 14 15 16 16 16 16 16 16 table ii. peak-to-peak resolution vs. input range and update rate for AD7709 peak-to-peak resolution in bits AD7709 on-chip registers both the AD7709 is controlled and configured via 4 on-chip registers as shown in figure 4 and described in more detail in the following section. in the following descriptions, set implies a logic 1 state and cleared implies a logic 0 state unless otherwise stated. 0a1 a0 din dout adc data register filter register din dout configuration register(24-bits) dout register select decoder status register comm unications register din din dout dout 0 oscpd stby r/w wen figure 4. AD7709 on-chip registers
AD7709 C12C rev. pra january 2001 preliminary technical data communications register- ( a1, a0= 0,0): the communications register is an 8-bit write-only register. all communications to the part must start with a write operation to the communications register. the data written to the communications register determines whether the next operation is a read or write operation, the type of read operation and to which register this operation takes place. for read or write operations, once the subsequent read or write operation to the selected register is complete, the inter- face returns to where it expects a write operation to the communications register. this is the default state of the inter- face, and on power-up or after a reset , the AD7709 is in this default state waiting for a write operation to the communications register. in situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with din high, returns the AD7709 to this default state by resetting the part. table iii outlines the bit designa- tions for the communications register. cr0 through cr7 indicate the bit location, cr denoting the bits are in the communications register. cr7 denotes the first bit of the data stream. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) stby(0) oscpd (0) 0 (0) 0(0) a1(0) a(0) table iii. communications register bit designations bit bit location mnemonic description cr7 wen write enable bit. a 0 must be written to this bit so the write operation to the communications register actually takes place. if a 1 is written to this bit, the part will not clock on to subse- quent bits in the register. it will stay at this bit location until a 0 is written to this bit. once a 0 is written to the wen bit, the next seven bits will be loaded to the communications register. cr6 r/ w a zero in this bit location indicates that the next operation will be a write to a specified regis- ter. a one in this position indicates that the next operation will be a read from the designated register. cr5 stby standby bit indication. set when its required to put the AD7709 in low power mode. clear to power up the AD7709. cr4 oscpd oscillator power down bit. if this bit is set , then placing the AD7709 in standby mode will stop the crystal oscillator reduc- ing the power drawn by these parts to a minimum. the oscillator will require 500ms to begin oscillating when the adc is taken out of standby mode. if this bit is cleared the oscillator is not shut off when the adc is put into standby mode and will not require the 500ms start-up time when the adc is taken out of standby. cr3 0 this bit must be programmed with a logic 0 for correct operation. cr2 0 this bit must be programmed with a logic 0 for correct operation. cr1-cr0 a1-a0 register address bits. these address bits are used to address the AD7709s registers and are outlined in table iv. table iv. AD7709 register selection table a1 a0 register 0 0 communications register during a write operation. 0 0 status register register during a read operation. 0 1 configuration register 1 0 filter register 1 1 adc data register
AD7709 C13C rev. pra january 2001 preliminary technical data status register - (a1,a0=0,0; power-on-reset = 00hex): the adc status register is an 8-bit read-only register. to access the adc status register, the user must write to the communications register selecting the next operation to be a read and load bits a1-a0 with 0,0. table v outlines the bit designations for the status register. sr0 through sr7 indicate the bit location, sr denoting the bits are in the status register. sr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy(0) 0(0) 0(0) 0(0) err (0) 0(0) stby(0) lock(0) table v. status register bit designations bit bit location mnemonic description sr7 rdy ready bit for the adc set when data is transferred to the adc data register. the rdy bit is cleared automatically a period of time before the data register is updated with a new conversion result or after the adc data register has been read. sr6 0 bit is automatically cleared . reserved for future use sr5 0 this bit is automatically cleared. reserved for future use sr4 0 this bit is automatically cleared. reserved for future use sr3 err adc error bit. this qualifying bit is set at the same at the rdy bit. when set it indicates that the result written to the adc data register has been clamped to all zeros or all ones. error sources include overrange and loss of lock. this bit is cleared at the same time as the rdy bit. sr2 0 this bit is automatically cleared. reserved for future use sr1 stby standby bit indication. when set it indicates that the AD7709 is in low power mode. cleared when the adc is powerd up. sr0 lock pll lock status bit. this bit is set if the pll has locked onto the 32khz crystal oscillator clock. the adc will not start conversion till this bit has been set. if the lock bit subsequently goes low the err bit will be set. configuration register(config) :(a1,a0 = 0,1; power-on-reset = 000000hex) the config register is a 24-bit register from which data can either be read or to which data can be written. this register is used to select the input channel and configure the input range, excitation current sources and i/o port.table xiii outlines the bit designations for this register. config24 through config0 indicate the bit location, config denoting the bits are in the configuration register. config24 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. a write to the config register has immediate effect and does not reset the the adcs. thus , if a current source is switched while the adc is converting the user will have to wait for the fullsettling time of the sinc^3 filter before getting a fully settled output. this equates to 4 outputs.
AD7709 C14C rev. pra january 2001 preliminary technical data config23 config22 config21 config20 config19 config18 config17 config16 psw1(0) psw2(0) i3en1 (0) i3en1(0) i2en1(0) i2en0(0) i1en1(0) i1en0(0) config15 config14 config13 config12 config11 config10 config9 config8 p4dig(0) p3dig(0) p2en(0) p1en(0) p4dat(0) p3dat(0) p2dat(0) p1dat(0) config7 config6 config5 config4 config3 config2 config1 config0 refsel(0) ch2(0) ch1(0) ch0(0) uni(0) rn2(0) rn1(0) rn0(0) table vi. configuration register bit designations bit bit location mnemonic description config23 psw1 power switch 1 control bit. set by user to enable power switch p1 to pwrgnd. cleared by user to enable use as a standard i/o pin. when adc is in standby mode the power switches are open. config22 psw2 power switch 2 control bit. set by user to enable power switch p2 to pwrgnd. cleared by user to enable use as a standard i/o pin. when adc is in standby mode the power switches are open. config21 i3en1 current source enable bits. used in conjunction with bit i3en0 to determine the function of current source i3 config20 i3en0 current source enable bits. used in conjunction with bit i3en1 to determine the function of current source i3 i3en1 i3en0 function 0 0 current source off 0 1 current source routed to iout1 pin. 1 0 current source routed to iout2 pin. 1 1 current source routed to gnd config19 i2en1 current source enable bits. used in conjunction with bit i2en0 to determine the function of current source i2 config18 i2en0 current source enable bits. used in conjunction with bit i2en1 to determine the function of current source i2 i2en1 i2en0 function 0 0 current source off 0 1 current source routed to iout1 pin. 1 0 current source routed to iout2 pin. 1 1 current source routed to gnd config17 i1en1 current source enable bits. used in conjunction with bit i1en0 to determine the function of current source i3 config16 i1en0 current source enable bits. used in conjunction with bit i1en1 to determine the function of current source i3 i1en1 i1en0 function 0 0 current source off 0 1 current source routed to iout1 pin. 1 0 current source routed to iout2 pin. 1 1 current source routed to gnd config15 p4dig digital input enable set by user to enable p4 as a digital input cleared by user to configure as pin p4/ain4 as analog input.
AD7709 C15C rev. pra january 2001 preliminary technical data config14 p3dig digital input enable set by user to enable p3 as a digital input cleared by user to configure as pin p3/ain3 as analog input. the default configuration is analog input. config13 p2en p2 digital output enable bit. set by user to enable p2 as a regular digital output pin. cleared by user to tristate p2 output. psw2 takes presedance over p2en. config12 p1en p1 digital output enable bit. set by user to enable p1 as a regular digital output pin. cleared by user to tristate p1 output. psw1 takes presedance over p1en. config11 p4dat digital input port data bit. p4dat is read only and will return a 0 if p4dig=0. if p4 is enabled as a digital input then the read back value indicates the status of pin p4. config10 p3dat digital input port data bit. p3dat is read only and will return a 0 if p3dig=0. if p3 is enabled as a digital input then the read back value indicates the status of pin p3. config9 p2dat digital output port data bit. p2 is digital output only. when the port is active as an output (p2en=1), then the value written to the this data bit appears at the output port. reading p2dat will return what was last written to the p2dat bit on the AD7709. config8 p1dat digital output port data bit. p1 is digital output only. when the port is active as an output (p1en=1), then the value written to the this data bit appears at the output port. reading p1dat will return what was last written to the p1dat bit on the AD7709. config7 refsel adc reference input select. cleared by user to select refin1(+) and refin1(-) as the adc reference. set by user to select refin2(+) and refin2(-) as the adc reference. config6 ch2 adc input channel selection bit. used in conjunction with ch1 and ch0 as shown in the analog input selection table. config5 ch1 adc input channel selection bit. used in conjunction with ch2 and ch0 as shown in the analog input selection table. config4 ch0 adc input channel selection bit. used in conjunction with ch2 and ch2 as shown in the analog input selection table. ch2 ch1 ch0 positive input negative input buffer 0 0 0 ain1 aincom positive analog input 0 0 1 ain2 aincom positive analog input 0 1 0 ain3 aincom positive analog input 0 1 1 ain4 aincom positive analog input 1 0 0 ain1 ain2 positive and negative analog inputs 1 0 1 ain3 ain4 positive and negative analog inputs 1 1 0 aincom aincom positive and negative analog inputs the final column indicates if the analog inputs are buffered or unbuffered. this determines the common mode input range on each input. if the input is unbuffered (aincom) the common mode input includes gnd. config3 uni unipolar/bipolar operation selection bit. set by user to enable unipolar operation with straight binary output coding i.e. zero differ- ential input will result in 0000hex output and a fullscale differential input will result in ffff hex output. cleared by user to enable pseudo bipolar operation and offset binary coding, negative fullscale differential input will result in an output code of 0000 hex, zero differential in- put will result in an output code of 8000hex and a positive fullscale differential input will result in an output code of ffff hex.
AD7709 C16C rev. pra january 2001 preliminary technical data config2 rn2 used in conjunction with rn1 and rn0 to select the analog input range. config1 rn1 used in conjunction with rn2 and rn0 to select the analog input range. config0 rn0 used in conjunction with rn2 and rn1 to select the analog input range. rn2 rn1 rn0 selected main adc input range (vref=2.5v) 0 0 0 20mv 0 0 1 40mv 0 1 0 80mv 0 1 1 160mv 1 0 0 320mv 1 0 1 640mv 1 1 0 1.28v 1 1 1 2.56v filter register:(a1,a0=1,0; power-on-reset = 00hex) the filter register is an 8-bit register from which data can either be read or to which data can be written. this register determines the amount of averaging performed by the sinc filter. table vii outlines the bit designations for the filter register. fr7 through fr0 indicate the bit location, fr denoting the bits are in the filter register. fr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. the number in this register is used to set the decimation factor and thus the output update rate for the adcs. the filter register cannot be written to by the user while the adc is active. the update rate is used for the adc is calculated as follows : f adc = 1 x 1 x f mod 3 8.sf where : fadc = adc output update rate fmod = modulator clock frequency= 32.768khz (main and aux adc) sf = decimal value written to sf register fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 sf7(0) sf6(1) sf5(0) sf4(0) sf3(0) sf2(1) sf1(0) sf0(1) table vii. filter register bit designations the allowable range for sf is 13dec to 255dec. examples of sf values and corresponding conversion rate (f adc ) and time (t adc ) are shown in table xii below. it should also be noted that both adc input channels are chopped to minimise offset errors. this means that the time for a single conversion or the time to the first conversion result is 2 x t adc . table xii. update rate vs sf word. adc data result register (data):(a1,a0=1,1; power-on-reset = 000000hex) the conversion result for the selected adc channel is stored in the adc data register (data). this register is 16-bits wide. this is a read only register. on completion of a read from this register the rdy bit in the status register is cleared. sf(dec) sf(hex) f adc (hz) t adc (ms) 13 0d 105.3 9.52 69 45 19.79 50.34 255 ff 5.35 186.77
AD7709 C17C rev. pra january 2001 preliminary technical data configuring the AD7709 on the AD7709 there are only four user accessable registers and these are configured via the serial interface. communica- tion with any of these registers is initiated by firstly writing to the communications register. the AD7709 starts convert- ing after a power up without the requiring any register to be written to. the defaults conditions are used and the AD7709 operates at a 20hz update rate offering 50 and 60hz rejection. figure 5 outlines a flow diagram of the sequence used to configure the registers on the AD7709 following a power-up. the flowchart shows two methods of determining when its valid to read the data register. the first method is hardware polling of the rdy pin and the second method involves software interrogation of bits in the status and mode registers. the flowchart details all the necessary programming steps required to initialize the adc and read data from the selected adc chan- nel following a power-on or reset.the steps can be broken down as follows: 1. configure and initialize the microcontroller or microprocessor serial port. 2. initialize the AD7709 by configuring the following registers: a)filter registers which determines the update rate. the AD7709 must be put into standby mode before writing to the filter register. b) configuration register to select the input channel to be converted, its input range and reference. this register is also used to configure the internal current sources, power switches and i/o port. both of these operations consist of a write to the communications register to specify the next operation as a write to a specif ied register. data is then written to this register. when each sequence is complete the adc defaults to waiting for another write t o the communications register to specify the next operation. 3) when configuration is complete the user needs to determine when its valid to read the data from the data register. this is accomplished by either polling the rdy pin (hardware polling) or by interrogating the bits in the status register (software polling). both are shown in the following flowchart. hardware polling software polling power-on/reset for AD7709 configure & initialize m c/ m p serial port write to communications register selecting next operation to be a write to the filter register (write 22hex to comms reg) write to filter register to configure the required update rate. write to communications register setting up next operation to be a write to the configuration register (write 01hex to comms reg) start write to configuration register to select input channel, input range and reference. current sources and i/o port can also be configured write to communications register setting up next operation to be a read from the status register write 40hex to comms register read status register no yes rdy=1 write to communications register setting up next operation to be a read of the data register. write 43hex to comms register software polling poll rdy pin no rdy low? write to communications register setting up next operation to be a read of the data register (write 43hex to comms register) read16-bit data result yes another read? no channel change no yes end hardware polling read data from output register read16-bit data result yes another read? no channel change no yes end figure 5. flowchart for configuring and reading from AD7709

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